• DocumentCode
    1366272
  • Title

    Neural networks for fast arbitration and switching noise reduction in large crossbars

  • Author

    Ghosh, Joydeep ; Hukkoo, Ajat ; Varma, Anjun

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • Volume
    38
  • Issue
    8
  • fYear
    1991
  • fDate
    8/1/1991 12:00:00 AM
  • Firstpage
    895
  • Lastpage
    904
  • Abstract
    A neural-network-based controller for the real-time arbitration of routing paths in large crossbar switches constructed from one-sided crosspoint chips is presented. This controller is suitable for a synchronous environment where a number of connection requests are simultaneously presented to the switch. The controller aims to maximize the effective bandwidth of the switch and to minimize the simultaneous-switching noise in the individual chips. The controller uses multiple winner-take-all networks coupled with some competitive-cooperative mechanisms to achieve the joint optimization. The effects of various network parameters are studied through simulation, and cases leading to nonoptimal solutions are analyzed. A hierarchical neural network controller for a packet-switched environment where connections are established and broken asynchronously is introduced. This controller provides almost the same level of performance as the first, but with significantly reduced computation for each connection request
  • Keywords
    VLSI; electronic switching systems; neural nets; competitive-cooperative mechanisms; computation reduction; fast arbitration; hierarchical neural network controller; joint optimization; large crossbar switches; large crossbars; multiple winner-take-all networks; neural-network-based controller; one-sided crosspoint chips; packet-switched environment; performance; real-time arbitration of routing paths; switching noise reduction; synchronous environment; Active noise reduction; Bandwidth; Intelligent networks; Multiprocessor interconnection networks; Neural networks; Noise reduction; Routing; Switches; Throughput; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.85631
  • Filename
    85631