A data-transition look-ahead DFF circuit for statistical reduction in power consumption

Author

Nogawa, Masafumi ; Ohtomo, Yusuke

Author_Institution

NTT Syst. Electron. Labs., Kanagawa, Japan

Volume

33

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

702

Lastpage

706

Abstract

A new data-transition look-ahead DFF (DL-DFF) that reduces the power consumption of CMOS LSI´s is proposed. The power consumption is reduced in accordance with the data-transition probability. The main feature of the DL-DFF is that the clock signal is deactivated when there are no data transitions. This reduces the power consumption when the data-transition probability is low. The power consumption of a DL-DFF is compared to that of a conventional one by measuring a test chip fabricated using a 0.25-μm CMOS/SIMOX process. It is found that a DL-DFF consumes less power than a conventional one when the data-transition probability is under 60%. For example, when the data-transition probability is 25%, it consumes 29% less power. Moreover, some suitable applications of a DL-DFF are presented

Keywords

CMOS logic circuits; SIMOX; flip-flops; large scale integration; 0.25 micron; CMOS LSI; DL-DFF; SIMOX process; clock signal deactivation; data transition probability; look-ahead D flip-flop circuit; low power circuit; power consumption; statistical reduction; CMOS logic circuits; Circuit synthesis; Clocks; Encoding; Energy consumption; Flip-flops; Laboratories; Power measurement; Probability; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.668984

Filename

668984