A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

Author

Yang, Chih-Kong Ken ; Farjad-Rad, Ramin ; Horowitz, Mark A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

33

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

713

Lastpage

722

Abstract

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-μm HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3× the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10^-14

Keywords

CMOS digital integrated circuits; digital phase locked loops; timing; transceivers; 0.5 micron; 250 MHz; 3.3 V; 4.0 Gbit/s; 500 MHz; HPCMOS process; PLL; bit error rate; digital phase-picking logic; multiple phases; on-chip VCO; oversampling; phase spacing; robust data recovery; serial link transceiver; tracking bandwidth; Bandwidth; Bit error rate; Bit rate; CMOS logic circuits; Clocks; Multiplexing; Phase locked loops; Robustness; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.668986

Filename

668986