Title :
Universal built-in self-test procedure for CMOS PLA´s
Author :
Ortega, J. ; Prieto, A. ; Lloris, A. ; Pelayo, F.
Author_Institution :
Dept. of Electron. & Comput. Technol., Granada Univ., Spain
fDate :
8/1/1991 12:00:00 AM
Abstract :
The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced
Keywords :
CMOS integrated circuits; built-in self test; integrated circuit testing; logic arrays; logic testing; AND plane; CMOS PLAs; CMOS technology; OR planes; all multiple stuck-open faults; built-in self-test; detects all simple stuck-open faults; fault coverage; hardware overhead complexity; high percentage of coverage; programmable logic array; test patterns; universal BIST procedure; universal test; Built-in self-test; Capacitors; Circuit theory; Circuits and systems; Computer networks; Inductors; Programmable logic arrays; Roundoff errors; Switches; Voltage;
Journal_Title :
Circuits and Systems, IEEE Transactions on
