A mode-changeable 2-D DCT/IDCT processor for digital VCR

Author

Paek, Seung-Kwon ; Kim, Ji-Heup ; Kwon, Byung-Sup ; Chung, Dae-Hyun ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

42

Issue

3

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

606

Lastpage

616

Abstract

In a digital VCR, the DCT/IDCT is performed by both the 8×8 mode and the 2×4×8 mode to improve the coding efficiency. A new 2-D DCT/IDCT processor which requires minimal hardware overhead for 8×8/2×4×8 mode change for a digital VCR is presented. The proposed DCT/TDCT processor uses a concurrent architecture and executes both the DCT and IDCT with 8×8 and 2×4×8 mode selection. This chip is implemented on the basis of the row-column decomposition scheme. The proposed architecture minimizes the hardware overhead for the 2×4×8 mode by sharing the same data path with the 8×8 mode as much as possible. The proposed architecture also reduces the hardware and the chip size by exploiting the table look-up method instead of the extra multiplication circuits in the weighting coefficients handling. The implemented DCT/IDCT processor satisfies the accuracy specification of digital VCR

Keywords

digital magnetic recording; digital signal processing chips; discrete cosine transforms; inverse problems; multiprocessing systems; table lookup; transform coding; video coding; video tape recorders; DCT/IDCT; accuracy specification; chip size reduction; coding efficiency; concurrent architecture; digital VCR; hardware size reduction; minimal hardware overhead; mode changeable 2D DCT/IDCT processor; processor chip; row-column decomposition; table look-up method; weighting coefficients; Arithmetic; Circuits; Discrete cosine transforms; Hardware design languages; Video compression; Video recording;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.536163

Filename

536163