Effective Gate Layout Methods for RF Performance Enhancement in MOSFETs

Transistor scaling with CMOS technology evolution results in f _max saturation in contrast to fT improvement. This letter presents effective improvement methods for such saturated f _max in the transistors fabricated by 45-nm low-standby-power CMOS technology. The primary parameter investigated is the gate layout structure through changing the gate interconnects into several folded structures. It is demonstrated that we can achieve f _max of above 500 GHz and f _max/fT ratio of 2.9 in the transistors through applying the proposed gate layout structures. Such high f _max results from the effective reduction in the gate resistance.