A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer

Author

Luo, Xiaorong ; Lei, Tianfei ; Wang, Yuangang ; Gao, Huanmei ; Fang, Jian ; Qiao, Ming ; Zhang, Wei ; Deng, Hao ; Zhang, Bo ; Li, Zhaoji ; Xiao, Zhiqiang ; Chen, Zhengcai ; Xu, Jing

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

Volume

30

Issue

10

fYear

2009

Firstpage

1093

Lastpage

1095

Abstract

Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/mum in the conventional devices on p-SOI layer to 27 V/mum, resulting in enhancement of the BOX electric field EI from 30 to 82 V/mum. Moreover, holes located between the depleted n-islands help to increase EI as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC.

Keywords

power integrated circuits; silicon-on-insulator; bottom-interface electric field; breakdown mechanism; buried n-islands; buried oxide layer; high-voltage integrated circuits; high-voltage n-channel LDMOS; p-type SOI layer; p-type silicon-on-insulator layer; Electric fields; high-voltage techniques; power semiconductor devices; silicon-on-insulator (SOI) technology;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2009.2028249

Filename

5235128