Reducing the MISR size

Author

Savir, Jacob

Author_Institution

PowerPC Dev. Center, IBM Corp., Austin, TX, USA

Volume

45

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

930

Lastpage

938

Abstract

Multiple-input signature registers (MISRs) are commonly used in built-in self-test (BIST) applications. The size of the MISR is dictated by the number of signals it has to compress. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Large size MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of reducing the MISR so that it samples multiple signals at every stage. Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. This paper analyzes all these issues; shows ways to reduce their negative effect, and compares the results to previously published proposals

Keywords

built-in self test; combinational circuits; logic testing; BIST; MISR; built-in self-test; detection probability; escape probability; multiple-input signature registers; pseudorandom test; testability; Built-in self-test; Circuit faults; Circuit testing; Compressors; Degradation; Fault detection; Hardware; Jacobian matrices; Sampling methods; Wiring;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.536235

Filename

536235