DocumentCode :
1366669
Title :
Optimal realization of sets of interconnection functions on synchronous multiple bus systems
Author :
Kulasinghe, Priyalal ; El-Amawy, Ahmed
Author_Institution :
Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA
Volume :
45
Issue :
8
fYear :
1996
fDate :
8/1/1996 12:00:00 AM
Firstpage :
964
Lastpage :
969
Abstract :
We develop a formal and systematic methodology for designing an optimal multiple bus system (MBS) realizing a set of interconnection functions whose graphical representation (denoted as IFG) is symmetric. The problem of constructing an optimal MBS for a given IFG is NP-hard. In this paper, we show that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest for the vast majority of important interconnection function sets. We present a particular partition (which can be found in polynomial time) on the edge set of a vertex symmetric IFG, that produces a symmetric MBS with minimum number of buses as well as minimum number of interfaces. We demonstrate several advantages of such an MBS over a direct-link architecture realizing the same IFG, in terms of the number of ports per processor, number of neighbors per processors, and the diameter
Keywords :
graph colouring; logic design; multiprocessor interconnection networks; Cayley color graph; MBS; NP-hard; bus minimization; interconnection function; interconnection functions; interface minimization; optimal design; polynomial time solutions; synchronous multiple bus systems; Color; Communication system control; Delay; Design methodology; Hypercubes; Manipulator dynamics; Message passing; Multiprocessor interconnection networks; Polynomials; Switches;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.536238
Filename :
536238
Link To Document :
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