Title :
Synthesis of delay fault testability circuits
Author :
Chakravarty, Sreejit
Author_Institution :
Dept. of Comput. Sci., New York Univ., Buffalo, NY, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be “hazard free delay fault testable” is presented. In contrast to existing results that consider either “single path propagating hazard free robust tests” or “general robust tests” we consider “multiple path propagating hazard free robust tests” in our analysis
Keywords :
circuit optimisation; delays; design for testability; fault diagnosis; logic testing; multivalued logic circuits; delay fault testability circuits; general robust tests; hazard free delay fault testable; logic synthesis systems; multilevel logic optimization transformations; multilevel unate circuit; multiple path propagating hazard free robust tests; single path propagating hazard free robust tests; testability enhancing properties; testability preserving properties; Circuit faults; Circuit synthesis; Circuit testing; Delay effects; Hazards; Logic circuits; Logic testing; Propagation delay; Robustness; System testing;
Journal_Title :
Computers, IEEE Transactions on
