Transistor transient studies including transcapacitive current and distributive gate resistance for inverter circuits

We examine two assumptions commonly used in analytical studies of inverter transient performances, that the transcapacitive current during a transient and the distributive gate resistance are negligible. We derive the additional delay time expressions which need to be added to the delay times calculated with such assumptions. In addition, we propose an equivalent lumped transistor which accurately models the transient behavior of the transistor with a distributive gate resistance