Layout-Dependent Strain Optimization for p-Channel Trigate Transistors

In this paper, we investigate the optimization of device layout and embedded source/drain (eS/D) shape profile for strain engineered 22-nm node Si and SiGe p-channel trigate field-effect transistors by finite-element method simulations. A nested trigate layout with dummy gates is found to retain the maximum channel stress for all three conduction planes. The tradeoff between achievable mobility enhancement and active device density for the nested trigate layout is also investigated in this paper. Next, the impact of the eS/D shape on the channel stress for all three conduction planes is studied, and the rounded eS/D shape is found to be the optimal shape contrary to the planar case with sigma-shaped eS/D. Finally, strained SiGe channel trigate transistors are investigated as a potential candidate for future technology nodes. The evolution of formation and relaxation of the average strain of the compressively strained SiGe channel is systematically studied as a function of fin formation, embedded S/D formation, and layout configuration.