DocumentCode :
1367654
Title :
TAO-BIST: A framework for testability analysis and optimization for built-in self-test of RTL circuits
Author :
Ravi, Srivaths ; Lakshminarayana, Ganesh ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Volume :
19
Issue :
8
fYear :
2000
fDate :
8/1/2000 12:00:00 AM
Firstpage :
894
Lastpage :
906
Abstract :
In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (>99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0% and 1.5%, respectively, for a bit-width of 16. These overheads decrease further with an increase in bit-width. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low
Keywords :
Boolean functions; application specific integrated circuits; built-in self test; circuit optimisation; delays; digital signal processing chips; fault diagnosis; integrated circuit testing; logic testing; microprocessor chips; ASICs; Boolean function; RTL circuits; TAO-BIST; application-specific instruction processors; application-specific programmable processors; benchmark circuits; built-in self-test; digital signal processors; fault coverage; justification/propagation information; minimal area overheads; register-transfer level controller-datapath circuits; regular-expression based high-level symbolic testability analysis; test application time; test enhancement solution; test enhancements; testability analysis; three-phased approach; Application specific integrated circuits; Application specific processors; Automatic testing; Boolean functions; Built-in self-test; Circuit faults; Circuit testing; Delay; Hardware; Information analysis;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.856976
Filename :
856976
Link To Document :
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