Title :
Test set compaction algorithms for combinational circuits
Author :
Hamzaoglu, Ilker ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fDate :
8/1/2000 12:00:00 AM
Abstract :
This paper presents a new algorithm, essential fault reduction, for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced automatic test pattern generation system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits
Keywords :
VLSI; automatic test pattern generation; combinational circuits; fault simulation; logic testing; MinTest; automatic test pattern generation system; combinational circuits; compact test sets; dynamic compaction algorithm; essential fault reduction; lower bounds; single stuck-at fault model; test set compaction algorithms; test set size; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Heuristic algorithms; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
