Title :
Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects
Author :
Dang, Bing ; Shapiro, Michael ; Andry, Paul ; Tsang, Cornelia ; Sprogis, Edmund ; Wright, Steven ; Interrante, Mario ; Griffith, Jonathan ; Truong, Van ; Guerin, Luc ; Liptak, Roger ; Berger, Daniel ; Knickerbocker, John
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nF/mm2 is achieved with two-layer Si interposer chip stacks.
Keywords :
CMOS integrated circuits; capacitors; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D silicon interposer chip; CMOS test chip; CMOS-compatible TSV interconnects; capacitance density; deep-trench decoupling capacitors; integrated decoupling capacitors; multilayer stacking; reliability test; three-dimensional chip stack; thru-silicon via interconnects; two-layer silicon interposer chip stacks; Capacitance; Capacitors; Integrated circuit interconnections; Resistance; Stacking; Three dimensional displays; Through-silicon vias; 3-D integration; Chip stack; integrated decoupling capacitors; thru-Si via (TSV);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2010.2084068
