Title :
Approaches to extra low voltage DRAM operation by SOI-DRAM
Author :
Eimori, Takahisa ; Oashi, Toshiyuki ; Morishita, Fukashi ; Iwamatsu, Toshiaki ; Yamaguchi, Yasuo ; Okuda, Fumihiro ; Shimomura, Kenichi ; Shimano, Hiroki ; Sakashita, Narumi ; Arimoto, Kazutami ; Inoue, Yasuo ; Komori, Shinji ; Inuishi, Masahide ; Nishimu
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
5/1/1998 12:00:00 AM
Abstract :
The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V
Keywords :
DRAM chips; MOS memory circuits; isolation technology; silicon-on-insulator; 0.5 micron; 1 V; 16 Mbit; 50 ns; body bias control; body tied MOSFET; circuit technology; dielectric film; dual gate MOSFET; extra low voltage operation; floating body MOSFET; high-speed SOI-DRAM; mesa isolation; process technology; stacked capacitor; Circuits; Dielectric films; Isolation technology; Leakage current; Low voltage; MOS capacitors; Parasitic capacitance; Random access memory; Thin film transistors; Voltage control;
Journal_Title :
Electron Devices, IEEE Transactions on
