Suspended SOI structure for advanced 0.1-μm CMOS RF devices

Author

Hisamoto, Digh ; Tanaka, Satoshi ; Tanimoto, Takuma ; Kimura, Shinichiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

45

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

1039

Lastpage

1046

Abstract

Modern silicon-on-insulator (SOI) technology and 0.1-μm-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-μm CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics

Keywords

CMOS integrated circuits; UHF integrated circuits; equivalent circuits; field effect MMIC; inductors; integrated circuit modelling; integrated circuit technology; silicon-on-insulator; sputter etching; 0.1 micron; 19.6 GHz; 2D simulation; CMOS RF devices; Si; buried oxide layer; etching stopper; gate-potential spread; potential shifts suppression; short-channel characteristics; short-channel immunity; standard Si ULSI fabrication processes; suspended SOI structure; suspended inductor; CMOS process; Chemical processes; Costs; Etching; Fabrication; Inductors; Radio frequency; Silicon on insulator technology; Substrates; Two dimensional displays;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.669522

Filename

669522