Toward advanced parallel processing: exploiting parallelism at task and instruction levels

Author

Fukuda, Akira ; Murakami, Kazuaki ; Tomita, Shinji

Author_Institution

Dept. of Inf. Syst., Kyushu Univ., Fukuoka, Japan

Volume

11

Issue

4

fYear

1991

Firstpage

16

Lastpage

19

Abstract

The status of two projects that entail the development of a reconfigurable parallel processor system with 128 Sparc microprocessors and a superscalar processor with four operations proceeding in parallel is discussed. The design principles, system configuration, processing element, network architecture, and memory architecture of the reconfigurable processors (called KRPP) are described. The operating system for KRPP is discussed. The architecture for the superscalar (called a dynamically hazard-resolved, statically code-scheduled, nonuniform superscalar) is presented.<>

Keywords

parallel architectures; parallel machines; KRPP; Sparc microprocessors; dynamically hazard-resolved; instruction levels; memory architecture; network architecture; nonuniform superscalar; operating system; parallel processing; parallelism; processing element; reconfigurable parallel processor system; statically code-scheduled; superscalar processor; system configuration; task levels; Application software; Computational modeling; Computer aided instruction; Concurrent computing; Data structures; MIMO; Parallel processing; Process control; Process design; VLIW;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.85721

Filename

85721