DocumentCode
1367952
Title
Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout
Author
Shiraishi, Yoichi ; Sakemi, Jun´Ya ; Fukuda, Kazuyuki
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
10
Issue
8
fYear
1991
fDate
8/1/1991 12:00:00 AM
Firstpage
982
Lastpage
993
Abstract
Three kinds of feedthrough assignment algorithm are suggested for CMOS logic cell layout, and their solutions and processing times are compared. One is based on the idea that the feedthrough requirement with fewest feedthrough candidates is first assigned. The second is an optimum algorithm that solves the problem by formalizing it as an integer programming problem. The third is a combination of the two, in which the first algorithm is applied until all of the uniquely determined feedthroughs are assigned, and then the second one is applied. The second and third algorithms attain the optimum solution, but the first one does- not. The deviation of the first algorithm from the optimum solution is shown to be within 3.5% of the optimum. and the cell area increases less than 3.5%. The processing times of the first and third algorithms are 1/27.5 and 1/3.0, respectively, on average, of that of the optimum one. Thus it is concluded that the first algorithm, although not optimum, is practical, and may well be incorporated into the feedthrough assignment process
Keywords
CMOS integrated circuits; circuit layout CAD; integer programming; integrated logic circuits; logic CAD; CAD; CMOS logic cell layout; feedthrough assignment algorithm; integer programming; optimum algorithm; Automatic logic units; CMOS logic circuits; CMOS process; CMOS technology; Chip scale packaging; Design methodology; Helium; Large scale integration; Logic design; Routing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.85736
Filename
85736
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