Title :
Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths
Author :
Kittl, J.A. ; Hong, Q.Z. ; Rodder, M. ; Breedijk, T.
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
5/1/1998 12:00:00 AM
Abstract :
A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 μm; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 μm, TiSi2 thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I/sub OFF/=1 nA/μm for nMOS and pMOS, respectively).
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit metallisation; ion implantation; molybdenum; rapid thermal processing; silicon; titanium compounds; 0.06 micron; 0.12 micron; 1.5 V; TiSi/sub 2/-Si:Mo; drive currents; gate lengths; preamorphization implants; rapid-thermal-processing step; scaled CMOS technologies; self-aligned silicide; sheet resistance; CMOS process; CMOS technology; Crystallization; Doping; Implants; MOS devices; Silicides; Thermal degradation; Thermal resistance; Thermal stability;
Journal_Title :
Electron Device Letters, IEEE
