An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

Author

Ouyang, Charles ; Ryu, Kyungsuk ; Milor, Linda ; Maly, Wojciech ; Hill, Gene ; Peng, Yeng-kaung

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

13

Issue

3

fYear

2000

fDate

8/1/2000 12:00:00 AM

Firstpage

286

Lastpage

292

Abstract

In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor

Keywords

chemical mechanical polishing; dielectric thin films; integrated circuit metallisation; integrated circuit modelling; CMP process; chemical mechanical polishing; deposited ILD profile; die level; hydrodynamic pressure; in-die variation; interlayer dielectric; layout pattern; microprocessor; model parameters; multilevel metal processes; multiple ILD thickness variation; physical parameters; polishing pad deformation; Analytical models; Chemical analysis; Chemical processes; Circuit simulation; Computational modeling; Deformable models; Dielectrics; Hydrodynamics; Semiconductor device modeling; Slurries;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.857937

Filename

857937