DocumentCode :
1369142
Title :
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
Author :
Yu, Hao ; Chu, Chunta ; Shi, Yiyu ; Smart, David ; He, Lei ; Tan, Sheldon X D
Author_Institution :
Berkeley Design Autom., Santa Clara, CA, USA
Volume :
18
Issue :
10
fYear :
2010
Firstpage :
1399
Lastpage :
1411
Abstract :
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp inverse-inductance elements by replacing inductive-branch current with flux. The state matrix under VNA is diagonal-dominant, sparse, and passive. To further explore the sparsity and hierarchy at the block level, a new matrix-stretching method is introduced to reorder coupled fluxes into a decoupled state matrix with a bordered block diagonal (BBD) structure. A corresponding block-structure-preserved model-order reduction, called BVOR, is developed to preserve the sparsity and hierarchy of the BBD matrix at the block level. This enables us to efficiently build and simulate the macromodel within a SPICE-like circuit simulator. Experiments show that our method achieves up to 7× faster modeling building time, up to 33× faster simulation time, and as much as 67× smaller waveform error compared to SAPOR [a second-order reduction based on nodal analysis (NA)] and PACT (a first-order 2×2 structured reduction based on modified NA).
Keywords :
circuit simulation; integrated circuit interconnections; integrated circuit modelling; matrix algebra; BBD structure; BVOR; PACT; SAPOR; SPICE-like circuit simulator; VNA; block-structure-preserved macromodeling; bordered block diagonal; inductive coupling; inverse inductance elements stamping; large-scale inductive interconnect dominant circuits; matrix stretching method; nodal analysis; second-order reduction; state matrix; Circuit simulation; Coupling circuits; Helium; Inductance; Integrated circuit interconnections; Large-scale systems; Mutual coupling; Power system interconnection; Power system modeling; Sparse matrices; Circuit simulation; high-speed interconnect model; model-order reduction;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2024343
Filename :
5238567
Link To Document :
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