DocumentCode :
1369405
Title :
SH4 RISC multimedia microprocessor
Author :
Arakawa, Fumio ; Nishii, Osamu ; Uchiyama, Kunio ; Nakagawa, Norio
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Volume :
18
Issue :
2
fYear :
1998
Firstpage :
26
Lastpage :
34
Abstract :
Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing
Keywords :
microprocessor chips; multimedia computing; reduced instruction set computing; special purpose computers; 3D graphics processing; RISC multimedia microprocessor; SH4; floating-point; vector instructions; Arithmetic; Decoding; Frequency; Logic; Microprocessors; Pipelines; Random access memory; Reduced instruction set computing; Registers; Voltage;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.671400
Filename :
671400
Link To Document :
بازگشت