Monte Carlo Study of Ultimate Channel Scaling in Si and In $_{\rm 0.3}$ Ga $_{\rm 0.7}$ As Bulk M

A detailed analysis of nonequilibrium electron transport in n-type Si and In_0.3Ga_0.7As MOSFETs scaled into ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of I_D-V_G characteristics for a template, 25-nm gate length Si MOSFET compared against previous results from various Monte Carlo device codes, and for an equivalent 25-nm gate length In_0.3Ga_0.7As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily during the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in III-V semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.