DocumentCode :
1369636
Title :
Hector: a hierarchically structured shared-memory multiprocessor
Author :
Vranesic, Zvonko G. ; Stumm, Michael ; Lewis, David M. ; White, Ron
Author_Institution :
Toronto Univ., Ont., Canada
Volume :
24
Issue :
1
fYear :
1991
Firstpage :
72
Lastpage :
79
Abstract :
The architecture of the Hector multiprocessor, which exploits current microprocessor technology to produce a machine with a good cost/performance tradeoff, is described. A key design feature of Hector is its interconnection backplane, which can accommodate future technology because it uses simple hardware with short critical paths in logic circuits and short lines in the interconnection network. The system is reliable and flexible and can be realized at a relatively low cost. The hierarchical structure results in a fast backplane and a bandwidth that increases linearly with the number of processors. Hector scales efficiently to larger sizes and faster processors.<>
Keywords :
computer architecture; multiprocessing systems; Hector; cost/performance tradeoff; fast backplane; hierarchically structured shared-memory multiprocessor; interconnection backplane; logic circuits; microprocessor technology; short critical paths; short lines; Aggregates; Backplanes; Bandwidth; Computer architecture; Costs; Hardware; Integrated circuit interconnections; Logic circuits; Microprocessors; Multiprocessor interconnection networks;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/2.67196
Filename :
67196
Link To Document :
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