A new hardware-efficient architecture for programmable FIR filters

Although much research has been done on efficient high-speed filter architectures, much of this work has focused on filters with fixed coefficients, such as Canonical Signed Digit coefficient filter architectures, multiplierless designs, or memory-based designs. In this paper, we focus on digit-serial, high-speed architectures with programmable coefficients. To achieve high performance goals, we consider both of algorithm level and architecture implementation level of FIR filters. In algorithm level, we reformulate the FIR formulation in bit-level and take the associative property of the addition in both the digit-serial multiplications and filter formulations. In architecture level, we considered issues to implement the reformulated results efficiently. The issues include addition implementation, data flow arrangements, and treatment of sign-extensions. Based on the above considerations, we can obtain a filter architecture with accumulation-free tap structure and properties of short latency, flexible pipelinability and high speed. Comparing the cost and performance with previous designs, we find that the proposed architecture reduces the hardware cost of a programmable FIR filter to only half that of previous designs without sacrificing performance