• DocumentCode
    1369742
  • Title

    A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem

  • Author

    Nocco, Sergio ; Quer, Stefano

  • Author_Institution
    Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
  • Volume
    29
  • Issue
    12
  • fYear
    2010
  • Firstpage
    2027
  • Lastpage
    2040
  • Abstract
    The task graph cost-optimal scheduling problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of binate covering problems, hinged within a bounded model checking paradigm. In this approach, each covering instance, providing a min-cost trace for a given schedule depth, can be solved with several strategies, resorting to minimum-cost satisfiability solvers or pseudo-Boolean optimization tools. Unfortunately, all direct resolution methods show very low efficiency and scalability. As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. This approach follows the “circuit cofactoring” strategy, as it exploits a powerful technique to capture a large set of solutions for any new SAT counter-example. The overall method is completed with a branch-and-bound heuristic which evaluates lower and upper bounds of the schedule length, to reduce the state space that has to be visited. Our results show that the proposed strategy significantly improves the blind binate covering schema, and it outperforms general purpose state-of-the-art tools.
  • Keywords
    Boolean algebra; computability; optimisation; scheduling; all-solution SAT solver; binate covering schema; bounded model checking paradigm; branch-and-bound heuristic; circuit cofactoring strategy; heterogeneous processors; interdependent tasks; minimum-cost satisfiability solvers; pseudoBoolean optimization tools; running rates; schedule length; scheduling puzzle; task graph cost-optimal scheduling; Computational modeling; Optimization; Processor scheduling; Program processors; Scalability; Schedules; Upper bound; Formal methods; SAT; satisfiability; scheduling; symbolic techniques;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2010.2061631
  • Filename
    5621035