Absolute minimization of completely specified switching functions

Author

Hong, Sung Je ; Muroga, Saburo

Author_Institution

Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

Volume

40

Issue

1

fYear

1991

fDate

1/1/1991 12:00:00 AM

Firstpage

53

Lastpage

65

Abstract

For the automated design of PLAs (programmable logic arrays) with a minimum size, computationally efficient procedures are needed that can minimize functions of a large number of variables. For such minimization procedures, excessively long processing time and an excessively large memory requirement are major problems to overcome. An absolute minimization procedure is presented for standard PLAs with reduced computation time and memory space. The improvement achieved by this procedure, which is based on the decomposition of ratio sets, is mainly due to the detection of all essential prime implicants during the derivation of inclusion functions and to the merger of two procedures previously published by R.B. Cutler and S. Muroga (1987) into one efficient procedure

Keywords

circuit CAD; logic arrays; logic design; minimisation of switching nets; PLAs; absolute minimisation; automated design; completely specified switching functions; computationally efficient procedures; memory space; prime implicants; programmable logic arrays; Computational efficiency; Computer science; Corporate acquisitions; Helium; Minimization methods; Programmable logic arrays;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.67320

Filename

67320