Analysis of the determination of the dimensional offset of conducting layers and MOS transistors

Author

Swaving, Sieger ; Van Der Klauw, Cornelis L M ; Joosten, Johannes J M

Author_Institution

Philips Components, Eindhoven, Netherlands

Volume

4

Issue

3

fYear

1991

fDate

8/1/1991 12:00:00 AM

Firstpage

174

Lastpage

182

Abstract

The limitations of methods to determine the dimensional offsets in VLSI processes are discussed. The authors give a straightforward quantitative analysis of those methods in which the number of measurement points is not greater than the number of unknowns in the equations. General equations are derived for errors that are made in the extraction of dimensional offsets of conducting layers and MOS transistors. It is shown that, due to a dramatic amplification of small deviations, large errors occur if the extraction is not done carefully. The analysis is applied to the determination of the width offset of conducting layers and to the determination of the MOS transistor channel length offset

Keywords

MOS integrated circuits; VLSI; integrated circuit technology; MOS transistors; VLSI processes; channel length offset; conducting layers; dimensional offset; errors; measurement; width offset; Contact resistance; Electrical resistance measurement; Equations; Fabrication; Geometry; MOSFETs; Measurement techniques; Process control; Solid modeling; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.85937

Filename

85937