DocumentCode
1370226
Title
A network flow approach to the reconfiguration of VLSI arrays
Author
Codenotti, Bruno ; Tamassia, Roberto
Author_Institution
Istituto di Elaborazione dell´´Inf., Consiglio Nazionale delle Ricerche, Pisa, Italy
Volume
40
Issue
1
fYear
1991
fDate
1/1/1991 12:00:00 AM
Firstpage
118
Lastpage
121
Abstract
A technique for reconfiguring a two-dimensional VLSI array with faulty cells is presented. A network flow model of the problem is used to provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that the algorithm has good performance in practice
Keywords
VLSI; fault location; systolic arrays; Manhattan model; VLSI arrays; fault-free array; faulty cells; functional cells; network flow approach; network flow model; reconfiguration; Assembly systems; Circuit faults; Fault tolerant systems; Integrated circuit interconnections; Joining processes; Semiconductor device modeling; Systolic arrays; Very large scale integration; Wafer scale integration; Wire;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.67329
Filename
67329
Link To Document