Design and implementation of bandpass delta-sigma modulators using half-delay integrators

Author

Chuang, Sean ; Liu, Huining ; Yu, Xianggang ; Sculley, Terry L. ; Bamberger, Roberto H.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

Volume

45

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

535

Lastpage

546

Abstract

Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-μm n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005π input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004π input bandwidth

Keywords

CMOS integrated circuits; integrating circuits; sigma-delta modulation; 2 micron; A/D converters; bandpass delta-sigma modulators; fourth-order architecture; half-delay integrators; input bandwidth; input modulation network; n-well double-poly double-metal CMOS process; signal-to-noise ratio; sixth-order topology; Bandwidth; CMOS process; Circuit stability; Circuit synthesis; Computer science; Delta modulation; Linearity; Process design; Quantization; Signal design;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.673635

Filename

673635