DocumentCode
1370436
Title
Steiner tree constructions in λ3-metric
Author
Li, Yuan Yuan ; Cheung, S.K. ; Leung, K.S. ; Wong, C.K.
Author_Institution
Dept. of Comput. Sci., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Volume
45
Issue
5
fYear
1998
fDate
5/1/1998 12:00:00 AM
Firstpage
563
Lastpage
574
Abstract
We consider Steiner minimal trees (SMT´s) in metrics defined by given orientations. The problem is motivated by wiring considerations of VLSI chips when the wiring direction is not restricted to only horizontal and vertical. In particular, we concentrate on the case when the given orientations form angles of 0°, 60°, and 120° (λ3-metric) since many interesting results can be obtained which may shed light on other metrics in the family. Specifically, we show that any SMT can be transformed to one with their Steiner points located on the grid points of a multilevel grid, where the number of levels can be quite small. Based on this result, we have developed a simulated annealing-based algorithm to generate near-optimal SMT´s. Empirical results and comparisons with Euclidean cases are also given
Keywords
VLSI; circuit layout CAD; integrated circuit layout; simulated annealing; trees (mathematics); wiring; Steiner tree constructions; VLSI chips; grid points; minimal trees; multilevel grid; simulated annealing-based algorithm; wiring considerations; Computer science; Costs; Euclidean distance; Industrial engineering; Large scale integration; Simulated annealing; Steiner trees; Surface-mount technology; Very large scale integration; Wires;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.673638
Filename
673638
Link To Document