An analog VLSI chip with asynchronous interface for auditory feature extraction

Author

Kumar, Nagendra ; Himmelbauer, Wolfgang ; Cauwenberghs, Gert ; Andreou, Andreas G.

Author_Institution

Center for Language & Speech Process., Johns Hopkins Univ., Baltimore, MD, USA

Volume

45

Issue

5

fYear

1998

fDate

5/1/1998 12:00:00 AM

Firstpage

600

Lastpage

606

Abstract

We present an analog VLSI chip intended to serve as a front end of a speech recognition system. The chip architecture is inspired by biological auditory models common to humans and primate vertebrates. We include experimental results on a 1.2-μm CMOS custom analog VLSI implementation and speech recognition results obtained from software simulations of the hardware on the TI-DIGITS database

Keywords

BiCMOS analogue integrated circuits; VLSI; analogue processing circuits; auditory evoked potentials; feature extraction; neural chips; sample and hold circuits; speech recognition equipment; 1.2 micron; BiCMOS prototype chip; CMOS custom analog VLSI implementation; TI-DIGITS database; analog VLSI chip; asynchronous interface; auditory feature extraction; auditory signal processing; autoadaptive comparator; basilar membrane; biological auditory models; chip architecture; cochlear filter bank; discrete-action potentials; encoding; neural networks; sample and hold; software simulations; speech recognition system frontend; zero-crossing time intervals; Biological system modeling; Feature extraction; Frequency; Humans; Natural languages; Power engineering computing; Robustness; Speech processing; Speech recognition; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.673642

Filename

673642