Title :
Clock-deskew buffer using a SAR-controlled delay-locked loop
Author :
Dehng, Guang-Kaai ; Hsu, June-Ming ; Yang, Ching-Yuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mW (not including off-chip driver´s) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 /spl mu/s, respectively.
Keywords :
CMOS integrated circuits; buffer circuits; clocks; delay lock loops; low-power electronics; 0.25 micron; 1.1 V; 100 MHz; 3.3 mW; CMOS chip; binary search method; clock deskew buffer circuit; clock distribution; lock time; successive approximation register controlled delay locked loop; synchronization; CMOS process; Clocks; Delay; Jitter; Power dissipation; Power measurement; Search methods; Synchronization; Time measurement; Voltage measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
