ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Author

Ker, Ming-Dou ; Chen, Tung-Yang ; Wu, Chung-Yu ; Chang, Hun-Hsien

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

35

Issue

8

fYear

2000

Firstpage

1194

Lastpage

1199

Abstract

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (/spl mu/m//spl mu/m) in a 0.35-/spl mu/m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only /spl sim/1.0 pF (including the bond-pad capacitance) for high-frequency applications.

Keywords

CMOS analogue integrated circuits; capacitance; current-mode circuits; electrostatic discharge; integrated circuit design; integrated circuit modelling; protection; 0.35 micron; 1.0 pF; 6 kV; ESD protection design; analog input/output pin; bond-pad capacitance; current-mode applications; device dimension; high-frequency applications; human body model; input capacitance; machine model; power-rails clamp circuit; silicided CMOS process; Biological system modeling; CMOS process; Capacitance; Circuits; Clamps; Electrostatic discharge; Humans; Pins; Protection; Semiconductor device modeling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.859509

Filename

859509