MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

Author

Singh, Hertej ; Lee, Ming-Hau ; Lu, Guangming ; Kurdahi, Fadi J. ; Bagherzadeh, Nader ; Filho, Eliseu M Chaves

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

Volume

49

Issue

5

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

465

Lastpage

481

Abstract

This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems

Keywords

parallel architectures; reconfigurable architectures; MorphoSys; coarse-grain; data-parallel; high-throughput; reconfigurable array; reconfigurable computing system; reconfigurable system; reconfigurable system-on-chip; Computer applications;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.859540

Filename

859540