Title :
An architecture for computing Zech´s logarithms in GF(2m)
Author :
Assis, F.M. ; Pedreira, C.E.
Author_Institution :
Univ. Fed. do Paraiba, Brazil
fDate :
5/1/2000 12:00:00 AM
Abstract :
In this paper, a new method for calculation of Zech´s logarithm in GF(2m) is presented. For a given element, the logarithm is calculated by bit operations performed on its binary representation. No look-up tables are used. The proposed method makes feasible the implementation of an universal-type device for finite field arithmetic
Keywords :
digital arithmetic; logic design; Zech logarithms; Zech´s logarithm; bit operations; discrete neural networks; finite field arithmetic; finite fields; universal-type device; Computer architecture;
Journal_Title :
Computers, IEEE Transactions on
