FPGA based implementation of high speed tunable notch filter using pipelining and unfolding

In this paper, we present a Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of tunable Infinite Impulse Response (IIR) notch filter. The basic 2^nd ordered tunable notch filter structure is implementable in Xilinx Virtex-5 FPGA with maximum clock frequency of ~80MHz. Here, we propose a FPGA based design of extremely high speed tunable notch filter effectively operating at maximum clock frequency of ~1200MHz with the help of Scattered-Look-Ahead (SLA) pipelining with power-of-2-decomposition approach, proper retiming and unfolding applied over its basic low-speed structure. To generalize its FPGA based design for specific speed up factor, a new efficient simpler approach utilizing Pascal´s Triangle is proposed to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed notch filter. The post place & route synthesis results for its FPGA design are obtained by generating VHDL code showing that proposed restructured notch filter can operate effectively greater than 1200MHz clock frequency meeting the present days´ certain industry´s needs.