New high-speed adaptive frame synchronisers incorporating postdetection processing techniques

Presents two new high-speed digital frame synchronisers incorporating adaptive operating strategies and postdetection processing techniques developed by the authors. These adaptive and postdetection processing frame synchronisers are shown to minimise both the false alarm probability and the misdetection probability. It is shown that the high speed can be achieved by means of time division multiplexing and a parallel implementation structure, thereby enabling low-speed integrated circuits to form the high-speed adaptive and postdetection processing frame synchronisers, which are capable of operating at bit rates as high as several hundred megabits per s.<>