Title :
Supplementary condition for STG-designed speed-independent circuits
Author_Institution :
Centre Suisse d´´Electron. et de Microtech. SA, Neuchatel, Switzerland
fDate :
4/2/1998 12:00:00 AM
Abstract :
Speed-independent CMOS circuits designed using a state transition graph (STG) method are speed-independent only if the delays of the input inverters are considered as zero-delays
Keywords :
CMOS logic circuits; delays; graph theory; logic design; timing; CMOS circuits; STG-designed speed-independent circuits; input inverter delay; state transition graph;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980458
