• DocumentCode
    1371199
  • Title

    Supplementary condition for STG-designed speed-independent circuits

  • Author

    Piguet, C.

  • Author_Institution
    Centre Suisse d´´Electron. et de Microtech. SA, Neuchatel, Switzerland
  • Volume
    34
  • Issue
    7
  • fYear
    1998
  • fDate
    4/2/1998 12:00:00 AM
  • Firstpage
    620
  • Lastpage
    622
  • Abstract
    Speed-independent CMOS circuits designed using a state transition graph (STG) method are speed-independent only if the delays of the input inverters are considered as zero-delays
  • Keywords
    CMOS logic circuits; delays; graph theory; logic design; timing; CMOS circuits; STG-designed speed-independent circuits; input inverter delay; state transition graph;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980458
  • Filename
    673754
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1371199