Configurable multiplier blocks for embedding in FPGAs

A new architecture for configurable blocks is proposed which can be used to construct multipliers. An array of these blocks is capable of being configured to perform any 4m bit×4n bit signed/unsigned binary multiplication. The blocks are designed to be embedded within a conventional FPGA structure to increase the functionality of the device by freeing valuable general reconfigurable resources, particularly when used in the area of image processing