Title :
Low-power and low-voltage D-latch
Author :
Liu Po Ching ; Ong Geok Ling
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst.
fDate :
4/2/1998 12:00:00 AM
Abstract :
A novel low-power and low-voltage static D-latch is presented using weak transistors where the driving capability is not crucial. Based on the HSPICE simulation with 0.8 μm technology file from IME, power consumption has been reduced by 11% to 34%. The lowest operating voltage is 1.6 V
Keywords :
SPICE; flip-flops; 0.8 micron; 1.6 V; HSPICE simulation; IME technology file; low-power low-voltage static D-latch; power consumption; weak transistor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980447
