Title :
Design of GF(2m) multiplier using its subfields
Author :
Yong Suk ; Park, Sang Kyu
Author_Institution :
Dept. of Electron. Commun. Eng., Hanyang Univ., Seoul, South Korea
fDate :
4/2/1998 12:00:00 AM
Abstract :
A design method of a GF(2m) multiplier using its subfields is presented. This method can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. It has an advantageous feature, namely that a trade-off between hardware complexity and delay time can be achieved
Keywords :
delays; multiplying circuits; sequential circuits; GF(2m) multiplier; bit-parallel multiplier; delay time; hardware complexity; sequential logic multiplier; subfields;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980521
