Quaternary voltage-mode CMOS circuits for multiple-valued logic

Author

Thoidis, I. ; Soudris, D. ; Karafyllidis, I. ; Christoforidis, S. ; Thanailakis, A.

Author_Institution

VLSI Design & Testing Centre, Democritus Univ. of Thrace, Xanthi, Greece

Volume

145

Issue

2

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

71

Lastpage

77

Abstract

A set of novel voltage-mode CMOS circuits for the implementation of multiple-valued logic (MVL) systems is introduced. The circuit level implementation of the multiple-valued logic operators: logical sum, logical product, level-up, level-down and level conversions are presented. The mathematical properties of the latter operator are formally proved, The proposed multiple-valued logic circuits exhibit zero static power consumption, do not use clocking, and function on any arithmetic base. The proposed circuits consist of appropriately constructed enhancement-mode and depletion-mode 1.5 μm MOSFETs. Simulation of the introduced quaternary logic voltage-mode CMOS circuits, using SPICE, indicates improved performance (higher speeds) compared to existing ones

Keywords

CMOS logic circuits; SPICE; circuit analysis computing; logic CAD; multivalued logic circuits; 1.5 micron; SPICE; arithmetic base; circuit level implementation; depletion-mode MOSFETs; enhancement-mode MOSFETs; level conversions; level-down; level-up; logical product; logical sum; multiple-valued logic; quaternary voltage-mode CMOS circuits; zero static power consumption;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19981763

Filename

674073