• DocumentCode
    1372311
  • Title

    An x86-64 Core in 32 nm SOI CMOS

  • Author

    Jotwani, Ravi ; Sundaram, Sriram ; Kosonocky, Stephen ; Schaefer, Alex ; Andrade, Victor F. ; Novak, Amy ; Naffziger, Samuel

  • Author_Institution
    AMD, Austin, TX, USA
  • Volume
    46
  • Issue
    1
  • fYear
    2011
  • Firstpage
    162
  • Lastpage
    172
  • Abstract
    This paper describes the 32 nm implementation of an AMD x86-64 core. It occupies 9.69 mm2, contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries´ 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs.
  • Keywords
    CMOS integrated circuits; Ge-Si alloys; silicon-on-insulator; AMD x86-64 core; CMOS; SOI; SiGe; dual strain liners; eSiGe; embedded silicon germanium; high-K metal gate technology; transistors; Arrays; Clocks; Delay; Logic gates; Metals; Transistors; 64-bit architecture; 8T RAMcell; Array design techniques; clock power reduction; electromigration; low power; power gating; power monitor;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2010.2080530
  • Filename
    5624589