Title :
Clock and data recovery circuit with two exclusive-OR phase frequency detector
Author :
Kim, Dong-Hee ; Kang, Jin-Ku
Author_Institution :
Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea
fDate :
8/3/2000 12:00:00 AM
Abstract :
A clock and data recovery circuit with a two exclusive-OR phase-frequency detector is proposed. The PFD generates the control signal for the voltage-controlled oscillator (VCO) in the phase-locked loop by comparing different phase clocks and input data. Simulations show that this circuit operates an input at data rate of 800 Mbit/s to 1.2 Gbit/s under 2.5 V using 0.25 μm CMOS technology
Keywords :
CMOS digital integrated circuits; digital phase locked loops; phase detectors; synchronisation; voltage-controlled oscillators; 0.25 micron; 2.5 V; 800 Mbit/s to 1.2 Gbit/s; CMOS technology; clock recovery circuit; data rate; data recovery circuit; exclusive-OR phase-frequency detector; input data; phase clocks; phase-locked loop; voltage-controlled oscillator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000977
