Title :
Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration
Author :
Haque, Yusuf ; Lewis, Donald E. ; Hales, Rex ; Kier, Ryan J. ; Johancsik, Tracy ; Watkins, Paul ; Picken, William ; Harper, Marcellus ; Dujari, Shyam
Author_Institution :
Crest Semicond., Inc., Woodside, CA, USA
Abstract :
A 16b/250 MS/s ADC employs two time-interleaved ADCs with key mismatch errors calibrated in the analog domain. The ADC achieves 73.4dB SNR and 88dBFS SFDR with a 170MHz input signal. It consumes 750mW power. Die size is 3.5mm × 3.5mm in a 0.18μm CMOS process.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; CMOS process; analog domain; die size; foreground calibration; hybrid voltage-current mode architecture; mismatch errors; power 750 mW; size 0.18 mum; time interleaved ADC; word length 16 bit; Bandwidth; Calibration; Capacitors; Linearity; Signal to noise ratio; Timing; ADC; calibration; interleaving;
Conference_Titel :
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
Conference_Location :
Venice Lido
Print_ISBN :
978-1-4799-5694-4
DOI :
10.1109/ESSCIRC.2014.6942021
