A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration

A 12-bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered in order to achieve higher energy efficiency, and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical opamp implementation, the power consumption of the residue amplifier was reduced by roughly 70% in the first two stages and by 50% in the remaining stages. The ADC was implemented in 40nm digital CMOS and shows a Schreier figure-of-merit of 157.4 dB at 1V supply, sampling at 195MS/s, with an SNDR/SFDR of 64.77dB/82dB.