DocumentCode :
137303
Title :
A 9.1–12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction
Author :
Hershberg, Benjamin ; Raczkowski, Kuba ; Vaesen, Kristof ; Craninckx, Jan
Author_Institution :
Imec, Leuven, Belgium
fYear :
2014
fDate :
22-26 Sept. 2014
Firstpage :
83
Lastpage :
86
Abstract :
A wide tuning range class-B VCO in 28nm CMOS targeted for software defined radio applications demonstrates a technique for minimizing device stress while simultaneously optimizing off-state Q in digitally switched tank capacitor cells. The proposed digital varactor structure can be implemented using only capacitors and NMOS transistors, resulting in a very compact layout. The VCO operates between 9.1 - 12.7 GHz, achieving a tuning range of 32% and phase noise of -163.2 dBc/Hz at 20 MHz offset referred to a 915 MHz carrier while consuming 9.5 mW for a FoM of -187 dBc/Hz.
Keywords :
CMOS analogue integrated circuits; MMIC oscillators; field effect MMIC; stress analysis; varactors; voltage-controlled oscillators; CMOS process; NMOS transistors; bottom-pinning bias technique; capacitors; device stress minimization; digital varactor stress reduction; digitally switched tank capacitor cells; frequency 9.1 GHz to 12.7 GHz; off-state Q optimization; phase noise; power 9.5 mW; size 28 nm; software defined radio; wide tuning range class-B VCO; CMOS integrated circuits; Stress; Transistors; Tuning; Varactors; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
Conference_Location :
Venice Lido
ISSN :
1930-8833
Print_ISBN :
978-1-4799-5694-4
Type :
conf
DOI :
10.1109/ESSCIRC.2014.6942027
Filename :
6942027
Link To Document :
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