Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC

Many low-power successive approximation register analog-to-digital converters (ADCs) use separate small capacitors, instead of the entire charge scaling (CS) capacitor arrays, to sample the analog inputs. While reducing power consumption, it makes these ADCs prone to gain errors and input range reduction caused by parasitic capacitance of the CS array. This paper presents an effective technique with negligible hardware overhead to address this problem. Simulation results are also presented to validate the proposed technique.